On a single sliver of silicon it integrates multiple CPU cores, a graphics processing unit, a digital signal processor, a neural processing unit, an image signal processor, as well as a modem and other specialized blocks of logic. The result tells control logic how many power PFETs to activate.Ī TYPICAL SYSTEM-ON-CHIP for a smartphone is a marvel of integration. In the basic digital design, an independent clock triggers a comparator that compares the reference voltage to V DD. It tries to make the output voltage (V DD) equal to the reference voltage by controlling the current through the power PFET. The basic analog low-dropout voltage regulator controls voltage through a feedback loop. Their LDOs are engaged to supply the cores with voltages that will save power. Cores 2 through 4, however, have less demanding workloads. Its head switch, really a group of transistors connected in parallel, is closed, bypassing the LDO and directly connecting Core 1 to V IN, which is supplied by an external power management IC. In this case, Core 1 has the highest performance requirement. Low-dropout voltage regulators (LDOs) allow multiple processor cores on the same input voltage rail (V IN) to operate at different voltages according to their workloads. Research groups in industry and academia have tested at least a dozen designs over the past few years, and despite some shortcomings, a commercially useful digital LDO may soon be in reach. What's more, the resulting digital LDOs could be much smaller than their analog counterparts and perform better in certain ways. If we could instead build LDOs-and perhaps other analog circuits-from digital components, they would be much less difficult to port than any other part of the processor, saving significant design cost and freeing up engineers for other problems that cutting-edge chip design has in store. The analog components that enable DVFS, especially a circuit called a low-dropout voltage regulator (LDO), don't scale down like digital circuits do and must basically be redesigned from scratch with every new generation. “Porting” a digital design from an old semiconductor process to a new one is no picnic, but it's nothing compared to trying to move analog circuits to a new process. We've grown accustomed to a near-yearly introduction of new processors with substantially more computational power, thanks to advances in semiconductor manufacturing. That's mainly because the clock-generation and voltage-regulation circuits are analog, unlike almost everything else on your smartphone SoC. The circuits that orchestrate DVFS strive to ensure a steady clock and a rock-solid voltage level despite the surges in current, but they are also among the most backbreaking to design. It's all done in an effort to balance computational performance with power consumption, something that's particularly challenging for smartphones.
Learn more →ĭynamic voltage and frequency scaling (DVFS), happens continually in the processor, called a system-on-chip (SoC), that runs your phone and your laptop as well as in the servers that back them.
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